1. Technical Field
The present invention relates to a method for forming a semiconductor device, and more particularly, to a method for forming a metal line of a semiconductor device in which a low dielectric constant material is used as an interlayer dielectric layer and a surface of the interlayer dielectric layer is treated with plasma to prevent moisture and ammonia from being adsorbed in the low dielectric constant material.
2. Discussion of the Related Art
Recently, the number of devices integrated into one fingernail-sized semiconductor chip has approached, and in some cases exceeded, 1×109. This number of devices integrated into one semiconductor chip increases by geometrical progression. To obtain both high-integration and a high-speed in such a device, it is necessary to improve the development the semiconductor chip in both structural and material aspects. The improvement in the structure of the semiconductor chip involves an increase in the number of metal layers. Also, a shallow trench isolation (STI) method is used for isolation between the devices. In such devices, the semiconductor chip is formed of materials including copper (Cu) and low-dielectric materials (Low-k).
Particularly, with the increase of high integration of a semiconductor device, the distance between metal lines has become gradually narrowed and metal lines having a multilevel structure have been required. Parasitic capacitance and parasitic resistance components existing either between adjacent metal line layers on one layer or between adjacent lower or upper metal line layers have arisen as important problems. The need for a multilevel metal line having minimal parasitic capacitance and parasitic resistance components has been required in the manufacture of a high integrated semiconductor device having improved operational speed.
To form metal lines having reduced parasitic capacitance and parasitic resistance components, either metal having a low specific resistance such as Cu or a material having a low dielectric ratio such as low-k dielectric material is required as a metal line material.
Particularly, Cu has advantages in view of low specific resistance, low cost and simplified process. Also, Cu has demonstrated electro-migration effects better than that of aluminum by at least ten times.
Instead of existing SiO2, a low dielectric constant material may be used to reduce power consumption and improve the speed of a semiconductor device. A material having a dielectric constant value ‘k’ less than 3 is used in a semiconductor device having a line width of 90 nm or below.
Hereinafter, a related art method for forming a metal line of a semiconductor device will be described with reference to the accompanying drawings.
FIG. 1A to FIG. 1E are sectional views illustrating related art process steps of forming a metal line of a semiconductor device.
First, as shown in FIG. 1A, an etch stop layer 12 is deposited on a semiconductor substrate in which a lower metal line layer 11 is formed. An interlayer dielectric layer 13 is thickly formed on the etch stop layer 12.
The etch stop layer 12 is formed of SiN, SiC, SiCN, or SiCO, and the interlayer dielectric layer 13 is formed of phosphorous silicate glass (PSG), boron phosphorous silicate glass (BPSG), undoped silicate glass (USG), fluorine doped silicate glass (FSG), SiOC, high density plasma (HDP), plasma enhanced-tetra ethyl ortho silicate (PE-TEOS), or spin on glass (SOG).
However, in a semiconductor device of 0.13 μm or less, Cu is used as a metal line layer and a low dielectric constant material such as low-k dielectric material is typically used as the interlayer dielectric layer 13 to minimize parasitic capacitance and parasitic resistance components.
At this time, if the low dielectric constant material is used as the interlayer dielectric layer, SiO2 is deposited on the interlayer dielectric layer 13 to additionally form a capping layer 15. that the capping layer becomes necessary because the low dielectric constant material has a low density and thus will adsorb a gas including moisture and ammonia in the air. The capping layer 15 serves to prevent the low dielectric constant material from adsorbing the gas.
Next, as shown in FIG. 1B, a photoresist is deposited on the interlayer dielectric layer 13 and then patterned by exposing and developing processes to form a photoresist pattern 14 so that a region for a via hole is opened.
Afterwards, as shown in FIG. 1C, the capping layer 15 and the interlayer dielectric layer 13 are sequentially dry etched using the photoresist pattern 14 as an etching mask to form the via hole 16. As a result, the etch stop layer 12 is exposed through the via hole 16.
Subsequently, as shown in FIG. 1D, the photoresist pattern 14 is removed by an ashing process and the etch stop layer 12 exposed through the via hole 15 is etched to open the lower metal line layer 11.
Then, the opened via hole 16 is filled with a metal material 17 such as Cu so that the metal material 17 contacts the lower metal line layer 11 through the via hole 16.
Finally, as shown in FIG. 1E, the overfilled metal material 17 is planarized by a chemical mechanical polishing (CMP) process. In this case, the metal material 17 is removed by the CMP process until the capping layer 15 is exposed. Thus, a via contact 20 that contacts the lower metal line layer 11 is formed. The lower metal line layer 11 will be electrically connected to an upper metal line layer to be formed later, through the via contact 20.
However, the related art method for forming a metal line of a semiconductor device has several problems.
Since the low dielectric constant material used as the interlayer dielectric layer can adsorb a gas including moisture and ammonia in the air, any ammonia adsorbed in the low dielectric constant material during the process is externally emitted which will disturb the patterning process for forming the metal line. This will prevent the proper formation of a metal line, which can adversely affect the yield. Also, if the low dielectric constant material adsorbs any moisture, a dielectric constant value of the low dielectric constant material will increase, further deteriorating characteristics of the device.
The capping layer is additionally deposited on the interlayer dielectric layer of the low dielectric constant value to prevent moisture and ammonia from being adsorbed in the interlayer dielectric constant material. However, since the capping layer is formed of SiO2 having a high dielectric constant value, parasitic capacitance is increased between a lower metal and an upper metal, thereby also deteriorating the performance of the device.
A photoresist less responsive to ammonia may be used as the interlayer dielectric layer. However, such a photoresist is expensive and thus increases the process cost.